1. Field of the Invention
The present invention relates to a System on Chip (SoC) system, and more particularly, to an SoC system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and fast control of peripheral devices by a processor.
The present invention is derived from the research supported by the IT R&D program of the Ministry of Information and Communication (Republic of Korea) and the Institute for Information Technology Advancement (Republic of Korea) [Project Management Number: 2006-S006-02, Project Title: Component/Module technology for Ubiquitous Terminals].
2. Discussion of Related Art
A conventional bus-based SoC communication architecture is simple and requires a low design cost. In this architecture, a master device occupying the bus can directly and rapidly transfer data with peripheral devices. However, the conventional SoC communication architecture can transfer data only through a single bus shared by several devices and thus can transfer only one piece of data at a time. In addition, the greater the number of masters, i.e., transmitters, the lower a bus occupation ratio of each master is. Such a reduction in the occupation ratio limits the transfer quantity of a master and thus is not appropriate for a multiprocessor-based system that must transfer a large amount of data between masters in a short time.
In particular, in the SoC architecture based on data transfer using a shared memory, a master cannot access the memory while another master is using the memory. AMBA 2.0 on-chip bus is an example of such a SoC architecture. According to AMBA 2.0 on-chip bus, when one master Intellectual Property (IP) module is occupying a physical bus, other master IP modules cannot perform communication. Therefore, such architecture does not solve a problem of a bandwidth constraint caused by sharing a physical wire when data is transferred between a master IP module and a slave IP module.
In order to solve the above problem, there is a method that applies characteristics of a network to chip design. An on-chip network device designed according to an on-chip network protocol includes a plurality of on-chip network interfaces and a switch. The on-chip network interface includes an up-sampler for sequentially transferring on-chip network signals input from an IP module supporting the on-chip network protocol to the switch, and a down-sampler for transferring in reverse order on-chip network signals input from the switch to the IP module.
The on-chip network architecture is intended to solve the problem that, when one master IP module has a bus grant, other master IP modules must wait to use the bus. In this architecture, when many master IP modules need to simultaneously use a bus to communicate with different slave IP modules, the master IP modules can simultaneously perform communication without waiting for a bus grant. Such architecture is intended to prevent an IP module from waiting to use a bus and smoothly transfer a large amount of data.
However, the architecture is complex, requires a high design cost, and is not appropriate for controlling a device requiring a short delay because of data transfer delay between a switch and a network interface.